1. Technical Field
Embodiments of the present disclosure relate to semiconductor devices and semiconductor systems.
2. Related Art
Efforts have been made in the development of semiconductor devices to have increased operation speeds and integration densities. For example, synchronous memory devices suitable for operating in synchronization with an external clock signal have been designed to improve operation speed.
Initially, single data rate (SDR) synchronous memory devices were proposed to enhance the operation speed of semiconductor memory devices. SDR synchronous memory devices receive or output the data in synchronization with rising edges of an external clock signal. Despite such advancements, high performance memory devices operating faster than the SDR synchronous memory devices are still needed for meeting the requirements of high-performance electronic systems.
As a response, double data rate (DDR) synchronous memory devices operating at a higher speed than SDR synchronous memory devices have been proposed. DDR synchronous memory devices may receive or output the data twice during a single cycle of an external clock signal. More particularly, DDR synchronous memory devices may receive or output the data in synchronization with rising edges as well as falling edges of the external clock signal. Thus, DDR synchronous memory devices may operate at a speed that is twice as high as that of SDR synchronous memory devices, even without an increase in the frequency of the external clock signal.
DDR synchronous memory devices may use a multi-bit pre-fetch scheme that internally processes multi-bit data at the same time. In the multi-bit pre-fetch scheme, multi-bit data that is input serially may be aligned in parallel in synchronization with a data strobe signal. The multi-bit data aligned in parallel may be simultaneously transmitted to memory cells by a write command signal.
Accordingly, what are needed are devices, systems, and methods that overcome these and other related deficiencies in the art.